Design and Implementation of a 12-Bit SAR ADC with Optimized Technology

Abstract

This research presents the complete design and implementation of a 12-bit successive approximation register analog-to-digital converter in 45nm CMOS technology. The converter achieves 10.39 effective bits at 100 MS/s sampling frequency while consuming 1.97 mW from a 1.8 V supply. Through systematic behavioral modeling and transistor-level optimization, the design addresses critical challenges in high-speed precision data conversion, including comparator noise mitigation and capacitor matching requirements. The implemented architecture employs a binary-weighted capacitive DAC with common-centroid layout techniques and a noise-optimized dynamic comparator. Comprehensive post-layout simulations verify robust performance across process corners, with the complete design occupying 0.42 mm² of silicon area. This work demonstrates a viable solution for modern mixed-signal systems requiring high-speed conversion with maintained accuracy in advanced technology nodes.