Closed-Loop EDA Verification with AI: Autonomous Planning for Adaptive Simulation

Abstract

The area of EDA verification faces continuous issues with static regression testing methods that are not adaptable to new emerging areas of coverage or unexpected fail points in testing cycles. Conventional chip design verification methodologies run pre-defined test suites without reactivity to interim results in real time, leading to suboptimal allocation of resources and slowed progress of coverage achievement. Autonomous planning tools based on chain of thought reasoning and reinforcement learning bring revolutionary potential to dynamic verification management. These cognitive planners are fully responsive to simulation results continuously and can dynamically adjust test execution plans based on interim outcomes. The closed-loop system allows directed test stimuli aimed at particular areas of uncovered functionality while keeping necessary testing baselines. Upon failure points, planners apply concentrated debugging flows and temporarily shift allocation of resources for root cause investigation. Detailed decision logging creates record linkage of autonomous actions triggered by core evidence in all phases and steps of chip design verification testing. Architecturally neutral tool development enables easy interconnection of various simulators and platforms of coverage on standardized interfaces. The dynamically adaptive paradigm of verification holds a great promise of accelerating convergence of testing coverage, improving allocation of computing resources on simulators, and decreasing human intervention points in integrated circuit debugging.