An Explainable AI-Driven Framework for Functional Verification and Hardware Trojan Detection in Next-Generation System-on-Chip Architectures

Abstract

The rapid growing complexity of next-generation System-on-Chip (SoC) architectures has sharply increased the problem of functional assurance and hardware security, especially on the detection of stealthy Hardware Trojans (HTs). Conventional methods of verification do not detect triggers of rare events as well, and have no transparency in decision making procedures. To overcome these drawbacks, this paper suggests an original Explainable Artificial Intelligence (XAI)-based framework to support unified functional verification and hardware Trojan detection of the SoC designs. The suggested implementation combines anomaly detection on a case of deep learning and interpretable mechanisms to report sensible information to design suspicious behavior. The framework codes on structural and functional characteristics derived using Register Transfer Level (RTL) and gate-level models, permitting the identification of rogue breaches at an early stage. In addition, the XAI models like feature attribution and attention visualization are introduced to promote the trust, debugability, and efficiency of verifying. The offered framework, in contrast to the traditional black-box AI models, is transparent, as the key elements and signal-tracing directions leading to the activities of Trojan are identified. This paper describes a scalable, technology-neutral architecture that can be incorporated into more current Electronic Design Automation (EDA) processes. The proposed framework will make the gap between AI-based security analysis and verification needs closer, which will create the path to more secure and reliable SoC design approaches.