Hardware Acceleration of Image Processing Algorithms Using Vedic Multiplication in VLSI

Abstract

The processing speed of the image processing operations is very high, and so efficient computation schemes are needed for high-speed computation with low power consumption. It is the common case with the majority of Very Large Scale Integration (VLSI) multiplication techniques that there is latency, power, and complexity involved with them. The work here discusses the implementation of Vedic Multiplication, an effective and high-speed arithmetic scheme, for accelerating image processing algorithms in VLSI circuits. The work comprises the integration of multipliers of Vedic mathematics into the highest-level image-processing tasks such as filtering, edge detection, and transformation functions. A comparison of the conventional process of multiplication shows that Vedic Multiplication drastically reduces processing time with low power consumption and chip area. Simulation and synthesis are carried out using Xilinx Vivado and computation of parameters of performance such as propagation delay, power dissipation, and area consumption. The results demonstrate that there are appreciable improvements in computational efficiency, and the process is apt for real-time image processing in applications like medical imaging, remote sensing, and object detection. Future work has included expanding the application to Field-Programmable Gate Arrays (FPGAs) and applying optimization techniques to enhance processing efficiency further.