Design and Evaluation of an Optimized CMOS Layout for SRAM with Enhanced Power and Area Efficiency

Abstract

Various SRAM cell architectures, such as 10T, 9T, 8T, and 7T, are explored to enhance performance and stability, each offering improvements in specific regions while involving certain trade-offs. The number of transistors can be reduced to optimize area utilization by incorporating dynamic CMOS logic, which still enables the maintenance of high performance. In the present research, a novel sleepy technique combined with Adaptive Voltage Scaling (AVS) is proposed to design a low-power SRAM aimed at minimizing power consumption through the use of multi-threshold CMOS (MTCMOS) circuits. The proposed SRAM integrates sleep transistors with an additional leakage current feedback transistor in its MTCMOS-based structure, achieving effective results with respect to key parameters such as delay, power, and area.